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固定邏輯器件/德州儀器（TI）/TI 德州儀器邏輯芯片 D 型觸發(fā)器 SN74LVC574APWR

商品名稱：TI 德州儀器邏輯芯片 D 型觸發(fā)器 SN74LVC574APWR

商品型號：SN74LVC574APWR

數(shù)據(jù)手冊：

品牌：德州儀器（TI）

封裝規(guī)格：TSSOP

商品類別：

二級分類：固定邏輯器件

商品批號：1427 1842

貨期：

商品編號：

商品重量：0.1kg

庫存數(shù)量：10000 個

單價：￥ 10000.0000 詢價

訂購量：

產(chǎn)品詳情
相關(guān)產(chǎn)品

質(zhì)量信息

RoHS	是
REACH	是
引腳鍍層/焊球材料	NIPDAU, SN
MSL 等級/回流焊峰值溫度	Level-1-260C-UNLIM

封裝信息

封裝 \| 引腳	TSSOP (PW) \| 20
包裝數(shù)量 \| 包裝：	2,000?\|?LARGE T&R
工作溫度范圍 (℃)	-40 to 125

德州儀器邏輯芯片 D 型觸發(fā)器 SN74LVC574A 的特性

Operate From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Specified From -40°C to 85°C, -40°C to 125°C, and -55°C to 125°C
Max tpd of 7 ns at 3.3 V
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
Support Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC)
Ioff Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22

2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)

德州儀器邏輯芯片 D 型觸發(fā)器 SN74LVC574A 的說明

The SN54LVC574A octal edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCCoperation, and the SN74LVC574A octal edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operation.

These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs.

A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

OE\ does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

These devices are fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.

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